The disclosure relates to a method of fabricating a semiconductor device, and more particularly to a nonvolatile memory device and a method of fabricating the same.
Nonvolatile memory devices are divided into a floating gate (FG) type and a charge trap type depending on the type of the electric charge storage layer. The floating gate type can keep electric charges into the floating gate as a form of free charges, and the charge trap type can keep electric charges in traps which are provided in the charge storage layer. The floating gate type includes a dielectric layer between control gates. The dielectric layer may include a stack structure of an oxide layer, a nitride layer and an oxide layer, i.e., an ONO layer or a high k dielectric layer.
The typical charge trap type nonvolatile memory device may include a MANOS structure, as shown in FIG. 1A.
FIG. 1A illustrates a cross-sectional view of a charge trap type nonvolatile memory device with a typical metal/aluminum oxide/nitride/oxide/silicon (MANOS) structure.
Referring to FIG. 1A, the MANOS structure includes a silicon substrate 11, a tunneling layer 12, a silicon nitride (Si3N4) layer 13, an aluminum oxide layer 14 and a metal layer 15. The tunneling layer 12 may include a silicon oxide layer.
The floating gate type nonvolatile memory device with an ONO structure may have a structure as shown in FIG. 1B.
FIG. 1B illustrates a cross-sectional view of a typical floating gate type nonvolatile memory device with an ONO structure. An isolation layer 22 is formed over a substrate 21 having trenches. More particularity, the isolation layer 22 is formed to fill the trenches of the substrate 31. A tunneling layer 23 and a floating gate 24 are sequentially formed over protruding portions of the substrate 21. Then, an ONO layer 25 and a control gate 26 are formed over the floating gate 24 and the isolation layer 22 in sequence.
Referring to FIG. 1B, a substantial magnitude of capacitance may be ensured since the ONO layer 25 and the control gate 26 are surrounding the floating gate 24. Due to this structure, the coupling ratio of the device may be increased. However, in a highly integrated nonvolatile memory device having a line width of 40 nm or less, an interference C between neighboring floating gates may occur. In order to overcome such drawbacks as interferences, the structure as shown in FIG. 1C may be suggested.
FIG. 1C illustrates a cross-sectional view of a floating gate type nonvolatile memory device with a typical inter poly dielectric (IPD) structure.
Referring to FIG. 1C, an isolation layer 32 is formed over a substrate 31 having trenches. More particularity, the isolation layer 32 is formed to fill the trenches of the substrate 31. A tunneling layer 33 and a floating gate (FG) 34 are sequentially formed over protruding portions of the substrate 31. The gap between neighboring floating gates 34 is filled with the isolation layer 32. An IPD 35 and a control gate (CG) 36 are sequentially formed over a planarized surface of the floating gate 34 and the isolation layer 32.
The capacitance area of the structure as shown in FIG. 1C may be decreased, when compared to the capacitance area of the structure as shown in FIG. 1A, since the IPD 35 and the control gate 36 are formed over the surface of the floating gate 34. Thus, the equivalent oxide thickness (EOT) of the IPD 35 should be decreased in order to increase its coupling ratio. In order to increase the coupling ratio, it is suggested to use a high-k dielectric layer having a greater dielectric constant than the ONO structure as an IPD layer.
However, since the silicon nitride layer (Si3N4) 13 is used as a charge storage layer in the typical MANOS structure, the silicon nitride layer 13 may not be removed. Furthermore, the low energy band gap of the aluminum oxide layer 14 that is used as a blocking layer and many trap site formed in the aluminum oxide layer 14 deteriorate the date retention characteristics of the nonvolatile memory devices.
Moreover, in the typical floating gate structure as shown in FIG. 1C, since most of the high-k dielectric layers have a low energy band-gap and many trap site, the device's speed characteristics in programming and erasing operations and data retention characteristics are deteriorated.
FIG. 2 is a graph illustrating the loss of electric charges in a data retention mode with respect to a nonvolatile memory device having a typical MONOS structure.
Referring to FIG. 2, in the data retention mode, an energy band has a slight tilt. The tilt is caused by an internal field owing to electron charges trapped in a charge storage layer. Thus, some of the electric charges are lost in the data retention mode since the electric charges trapped in the charge storage layer are drained off to the blocking layer.
In general, when an electron having the highest trap level in the silicon nitride layer is in a thermally excited state, the excited electron (e) transfers to the conduction band EC of the silicon nitride layer.
At first, the electron (e) transferred to the conduction band is likely to jump over the band offset (BO) {circle around (1)} since the band offset (BO) between the conduction bands of the silicon nitride layer and the aluminum oxide layer is small.
Then, the electron (e) that has been transferred to the conduction band EC of the silicon nitride layer is drained off through the many traps T {circle around (2)}.
The above-mentioned loss of the electric charges may occur in floating gates. That is, the electric charges stored in the floating gate may be lost owing to the use of a high-k dielectric layer having a low energy band gap and many trap sites.